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TNETV1002IDZHK 数据表(PDF) 9 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 9 Page - Texas Instruments |
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9 / 102 page  Tables ix June 2001 -- Revised December 2002 SPRS180C List of Tables Table Page 2--1 Pin Assignments for the GHK Package 4 ................................................ 2--2 Terminal Functions 7 ................................................................. 2--3 Internal Pullup/Pulldown Terminal List 11 ................................................. 3--1 CPU Memory-Mapped Registers 17 ..................................................... 3--2 Peripheral Memory-Mapped Registers 18 ................................................. 3--3 McBSP Control Registers and Subaddresses 19 .......................................... 3--4 Bank-Switching Control Register (BSCR) Bit Fields 20 ....................................... 3--5 Relationship Between BNKCMP and Bank Size 21 .......................................... 3--6 State of Signals When External Bus Interface is Disabled (EXIO = 1) 21 ....................... 3--7 Sample Rate Generator Clock Source Selection 22 ......................................... 3--8 DMA Interrupts 23 ...................................................................... 3--9 DMA Synchronization Events 24 ......................................................... 3--10 DMA Channel Interrupt Selection 24 ...................................................... 3--11 DSP Clock Scaler Values and Minimum REFCLK Frequencies 26 ............................. 3--12 DSP Interrupt Mapping 27 ............................................................... 3--13 IFR and IMR Register Bit Fields 28 ....................................................... 4--1 MCU Memory Space 30 ................................................................ 4--2 GPIO Control/Status Bits 38 ............................................................. 4--3 GPIO_IRQ Bits Definition 38 ............................................................. 4--4 MCU Peripheral Interrupt Mapping 41 ..................................................... 4--5 Reset Management 43 .................................................................. 4--6 DSP Boot Memory 44 ................................................................... 4--7 Emulation Mode Selection 44 ............................................................ 4--8 JTAG TAP Controller Instruction Register Lengths 45 ....................................... 6--1 Thermal Resistance Characteristics 49 .................................................... 6--2 Divide-By-Two/Divide-By-Four Clock Option Timing Requirements 50 ......................... 6--3 Divide-By-Two/Divide-By-Four Clock Option Switching Characteristics 50 ...................... 6--4 Multiply-By-N Timing Requirements 51 .................................................... 6--5 Multiply-By-N Switching Characteristics 51 ................................................. 6--6 Memory Read Timing Requirements 52 ................................................... 6--7 Memory Read Switching Characteristics 52 ................................................ 6--8 Memory Write Switching Characteristics 54 ................................................ 6--9 Parallel I/O Port Read Timing Requirements 56 ............................................. 6--10 Parallel I/O Port Read Switching Characteristics 56 ......................................... 6--11 Parallel I/O Port Write Switching Characteristics 57 ......................................... 6--12 Ready Timing For Externally Generated Wait-States Timing Requirements 58 .................. 6--13 Reset and Interrupt Timing Requirements 61 ............................................... 6--14 DSP_IAQ and DSP_IACK Switching Characteristics 62 ...................................... 6--15 DSP_XF and DSP_TOUT Switching Characteristics 63 ...................................... 6--16 McBSP Receive and Transmit Timing Requirements 64 ..................................... 6--17 McBSP Receive and Transmit Switching Characteristics 65 .................................. 6--18 McBSP General-Purpose Timing Requirements 67 .......................................... 6--19 McBSP General-Purpose Switching Characteristics 67 ...................................... |
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