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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TNETV1002IDZHK 数据表(PDF) 7 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 7 Page - Texas Instruments |
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7 / 102 page  Figures vii June 2001 -- Revised December 2002 SPRS180C List of Figures Figure Page 2--1 5471 Functional Block Diagram 3 ........................................................ 2--2 257-Ball GHK Package (Bottom View) 4 .................................................. 3--1 5471 DSP Subsystem Functional Block Diagram 12 ......................................... 3--2 Memory Map for DSP Accesses (DSP_APIBN = 1 or ABMDIS = 1) 14 ......................... 3--3 API Boot Mode Memory Map for DSP Accesses (DSP_APIBN = 0 and ABMDIS = 0) 15 .......... 3--4 DSP Extended Program Memory Map 16 .................................................. 3--5 Bank-Switching Control Register (BSCR) 19 ................................................ 3--6 Pin Control Register (PCR) 22 ............................................................ 3--7 IFR and IMR Registers 28 ................................................................ 4--1 5471 MCU Subsystem Functional Block Diagram 29 ......................................... 4--2 Ethernet Interface Block Diagram 33 ....................................................... 4--3 Clock Management Module 42 ............................................................ 6--1 3.3-V Test Load Circuit 49 ................................................................ 6--2 External Divide-by-Two Clock Timing 50 .................................................... 6--3 External Multiply-by-One Clock Timing 51 .................................................. 6--4 Memory Read 53 ....................................................................... 6--5 Memory Write 55 ........................................................................ 6--6 Parallel I/O Port Read 56 ................................................................. 6--7 Parallel I/O Port Write 57 ................................................................. 6--8 Memory Read With Externally Generated Wait-States 58 ..................................... 6--9 Memory Write With Externally Generated Wait-States 59 ..................................... 6--10 I/O Read With Externally Generated Wait-States 59 ......................................... 6--11 I/O Write With Externally Generated Wait-States 60 ......................................... 6--12 Interrupt Timing 61 ...................................................................... 6--13 DSP_IAQ and DSP_IACK Timings 62 ...................................................... 6--14 DSP_XF Timing 63 ...................................................................... 6--15 DSP_TOUT Timing 63 ................................................................... 6--16 McBSP Receive Timings 66 .............................................................. 6--17 McBSP Transmit Timings 66 .............................................................. 6--18 McBSP General-Purpose I/O Timings 67 ................................................... 6--19 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 68 ........................ 6--20 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 69 ........................ 6--21 McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 70 ........................ 6--22 McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 71 ........................ 6--23 SDRAM Read Command (CAS Latency 3) 72 ............................................... 6--24 SDRAM Write Command 73 .............................................................. 6--25 SDRAM Active Command 73 ............................................................. 6--26 SDRAM Precharge Command 74 ......................................................... |
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