TNETV1002IDZHK datasheet(50/102 Pages) TI1

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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

4.3.6.2

TIMER0 as a Watchdog Timer

By default, TIMER0 is configured as a watchdog timer. The watchdog is designed to detect user programs

stuck in infinite loops resulting in loss of program control or “runaway” programs. When configured as a

watchdog counter, TIMER0 will reset the MCU subsystem if it counts down to zero. The MCU’s reset

initialization code may examine the WATCHDOG_STAT register to determine if a MCU reset was caused by

the Watchdog.

The user program should write periodically into LOAD_TIM register before the counter reaches 0 in order to

reload the timer with this new value. A LOAD_TIM write is taken into account only if the new loaded value is

different from the previous one. When the watchdog counter reaches 0, it resets the MCU core and all the

MCU subsystem peripherals.

On power up, the watchdog is enabled and the value loaded into LOAD_TIM register is set to the maximum

value (0xFFFF) and PTV is set to seven. This gives to user a time of 16,777,216 * tclk to switch to normal timer

mode or to set a different watchdog timer time out to Timer0.

If a programmer does not want to have this default watchdog functionality, he must write a specific sequence

into a dedicated register (TIMER_MODE) in order to configure it as a general-purpose timer.

Disabling TIMER0 Watchdog Function

Timer0 may be configured as a general-purpose timer by writing a predefined sequence (0xF5 followed by

0xA0) in the WATCHDOG_DIS bits of the CNTL_TIMER0 register. If the watchdog disable function sees a

write to CNTL_TIMER0 with WATCHDOG_DIS set to 0xF5, it begins watching for another write to

CNTL_TIMER0 with WATCHDOG_DIS set to 0xA0. If WATCHDOG_DIS in the next write is 0xA0, TIMER0

is set for general-purpose mode. If the next write is instead 0xF5, TIMER0 remains in watchdog mode and

the disable function begins watching again for 0xF5.

Re-enabling TIMER0 Watchdog Function

To switch TIMER0 from general-purpose timer mode to watchdog timer mode, write a ‘1’ in the WATCHDOG

bit of the CNTL_TIMER0 register. When WATCHDOG is set to 1, the LOAD_TIM value is forced to 0xFFFF.

Due to internal sequencing, the MCU code should wait at least three timer clock periods before re-initializing

LOAD_TIM or PVT to values that meet system watchdog timing needs.

4.3.7 MCU Interrupt Handler

The MCU subsystem interrupt handler prioritizes and masks interrupts from up to 16 MCU subsystem

interrupt sources (IRQ0–15). It also steers these interrupts to the MCU’s two interrupt inputs: ARM_IRQ

(low-priority interrupt request) and ARM_FIQ (fast interrupt request). It receives interrupts from both internal

modules and the external chip environment. External interrupts to the MCU subsystem interrupt handler may

be provided through GPIO and/or KBGPIO pins.

Each interrupt source has an interrupt level register (ILR) which defines the priority of the corresponding

interrupt. When multiple interrupts are pending, the interrupt with the highest-priority interrupt level register

value is sent to the MCU first. In the case of multiple pending interrupts with identical ILR priority values (with

no other pending interrupts with higher priority), the highest interrupt number is sent to the MCU first.

Each interrupt source can be individually routed to one of the two input interrupt lines of the MCU, by properly

setting the FIQ bit in the interrupt’s ILR_IRQ_n register.

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