TNETV1002IDZHK datasheet(64/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.6.2 Memory Write

Table 6--8 assumes testing over recommended operating conditions with DSP_MSTRB = 0 and H = 0.5tc(CO)

(see Figure 6--5).

Table 6--8. Memory Write Switching Characteristics†

PARAMETER

MIN

MAX

UNIT

td(CLKH-A)

Delay time, DSP_CLKOUT high to address valid‡

1.5

11.5

td(CLKL-A)

Delay time, DSP_CLKOUT low to address valid§

1.5

11.5

td(CLKL-MSL)

Delay time, DSP_CLKOUT low to DSP_MSTRB low

1.5

11.5

td(CLKL-D)W

Delay time, DSP_CLKOUT low to data valid

1.5

11.5

td(CLKL-MSH)

Delay time, DSP_CLKOUT low to DSP_MSTRB high

1.5

11.5

td(CLKH-RWL)

Delay time, DSP_CLKOUT high to DSP_R/W low

1.5

11.5

td(CLKH-RWH)

Delay time, DSP_CLKOUT high to DSP_R/W high

1.5

11.5

td(RWL-MSTRBL)

Delay time, DSP_R/W low to DSP_MSTRB low

H-- 3

H+ 3

th(A)W

Hold time, address valid after DSP_CLKOUT high‡

1.5

11.5

th(D)MSH

Hold time, write data valid after DSP_MSTRB high

H--3

H+3§

tw(SL)MS

Pulse duration, DSP_MSTRB low

2H--3

tsu(A)W

Setup time, address valid before DSP_MSTRB low

2H--3

tsu(D)MSH

Setup time, write data valid before DSP_MSTRB high

2H--3 2H+3§

ten(D--RWL)

Enable time, data bus driven after DSP_R/W low

H--3

tdis(RWH--D)

Disable time, DSP_R/W high to data bus high impedance

† Address, DSP_PS, and DSP_DS timings are all included in timings referenced as address.

‡ In the case of a memory write preceded by a memory write

§ In the case of a memory write preceded by an I/O cycle

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