TNETV1002IDZHK datasheet(36/102 Pages) TI1

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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

Table 3--11. DSP Clock Scaler Values and Minimum REFCLK Frequencies

k (SCALER)

MINIMUM REFCLK

FREQUENCY (MHZ)

k = n, for integer values of n between 1 and 15, inclusive

k = 0.5 * n, for integer values of n between 1 and 15, inclusive

k = 0.25 * n, for integer values of n between 1 and 15, inclusive

When in DIV mode, the PLL minimum input frequencies do not apply.

The PLL_DSP output frequency is dynamically selected by the contents of the memory-mapped

DSP_CLKMD peripheral register. The initial settings for this register are controlled by a memory-mapped

subsystem’s maximum operating frequency as defined in the parametric portion of this data manual.

3.5

DSP Power Management

The DSP subsystem has three power-down modes, which are activated by the IDLE1, IDLE2, and IDLE3

instructions. In these modes, the C54x DSP core enters a dormant state and dissipates considerably less

power than in normal operation.

The IDLE1 mode halts all DSP activities except the DSP system clock. Because the system clock remains

applied to the DSP subsystem peripheral modules, the DSP peripheral circuits continue operating and the

DSP_CLKOUT pin remains active. Thus, peripherals such as serial ports and timers can take the DSP out

of its power-down state.

The IDLE2 mode halts the DSP subsystem peripherals as well as the DSP core, but the DSP subsystem’s

phase-locked loop clock multiplier will remain active to allow for a rapid resume from IDLE2. Because the DSP

subsystem peripherals are stopped in this mode, they cannot be used to generate the interrupt to wake up

the C54x as with IDLE1. However, power is significantly reduced because the device is completely stopped.

To terminate IDLE2, activate either RESET or DSP_INT0 with a pulse that meets the requirements defined

in the parametric section of this data manual. Note that RESET assertion will cause the MCU subsystem to

hold the DSP subsystem in reset.

The IDLE3 mode functions like IDLE2 but it also halts the DSP phase-locked loop (PLL) circuit. IDLE3 is used

to achieve the lowest possible DSP power consumption. This mode reduces power dissipation more than

IDLE2. Furthermore, the IDLE3 state allows you to reconfigure the DSP PLL externally if the system requires

the C54x to operate at a lower speed to save power. To terminate IDLE3, activate RESET or DSP_INT0 with

a pulse that meets the requirements defined in the parametric section of this data manual. Note that RESET

assertion will cause the MCU subsystem to hold the DSP subsystem in reset.

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