TNETV1002IDZHK datasheet(35/102 Pages) TI1

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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

SAM is the default configuration when the DSP exits from a reset phase. SAM is normally selected whenever

the DSP is in normal operating mode or in IDLE 1. HOM is normally selected before the DSP is placed in IDLE2

or IDLE3.

3.4.4 DSP External Memory Interface

The 5471 external memory interface is largely identical to that of the 5409. Significant differences include the

lack of a MP/MC pin, and multiplexing of DSP_MSC, DSP_IAQ, DSP_IACK, and DSP_CLKOUT functions

on KBGPIO pins.

3.4.5 DSP Software-Programmable Wait-State Generator

The 5471 DSP subsystem’s software wait-state generator is compatible with the 5409. Wait-states

programmed in the SWWSR register apply to both DSP-generated and DMA-generated cycles to external

memory peripherals on the DSP’s XIO bus.

3.4.6 DSP Timer

The 5471 DSP timer is identical to that found on the 5409.

3.4.7 DSP Clocking

The DSP subsystem is capable of operating in DIV mode and PLL (normal) mode. The MCU may program

the initial DSP initial clocking mode, and DSP code may change to other clocking modes. The DSP controls

the clocking mode of operation via the settings in the CLKMD register.

The DSP subsystem’s PLL module, when operating in PLL (normal) mode, provides a multiplied version of

the REFCLK input clock as the DSP subsystem clock. The PLL can multiply by integer values between 1

and 15, by 0.5*n (for integer values of n between 1 and 15, inclusive), or by 0.25*n (for integer values of n

between 1 and 15, inclusive). To ensure that the PLL locks to the input frequency, the input clock frequency

must meet the minimum frequency as shown for each set of scaling values in Table 3--11.

TNETV1002IDZHK 数据表(PDF) 35 Page - Texas Instruments