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TNETV1002IDZHK 数据表(PDF) 66 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 66 Page - Texas Instruments |
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66 / 102 page  Electrical Specifications 56 June 2001 -- Revised December 2002 SPRS180C 6.6.3 Parallel I/O Port Read Timing Requirements Table 6--9 and Table 6--10 assume testing over recommended operating conditions with DSP_IOSTRB =0 and H = 0.5tc(CO) (see Figure 6--6). Table 6--9. Parallel I/O Port Read Timing Requirements† MIN MAX UNIT ta(A)IO Access time, read data access from address valid‡ 3H--15 ns ta(ISTRBL)IO Access time, read data access from DSP_IOSTRB low‡ 2H--15 ns tsu(D)IOR Setup time, read data before DSP_CLKOUT high 4 ns th(D)IOR Hold time, read data after DSP_CLKOUT high 0 ns th(ISTRBH-D)R Hold time, read data after DSP_IOSTRB high 0 ns † Address and DSP_IS timings are included in timings referenced as address. ‡ This access timing reflects a zero wait-state timing. Table 6--10. Parallel I/O Port Read Switching Characteristics† PARAMETER MIN MAX UNIT td(CLKL-A) Delay time, DSP_CLKOUT low to address valid 1.5 11.5 ns td(CLKH-ISTRBL) Delay time, DSP_CLKOUT high to DSP_IOSTRB low 1.5 11.5 ns td(CLKH-ISTRBH) Delay time, DSP_CLKOUT high to DSP_IOSTRB high 1.5 11.5 ns th(A)IOR Hold time, address after DSP_CLKOUT low 1.5 11.5 ns † Address and DSP_IS timings are included in timings referenced as address. DSP_IS DSP_R/W DSP_IOSTRB DSP_D[15:0] DSP_A[19:0] DSP_CLKOUT th(A)IOR td(CLKH-ISTRBH) th(D)IOR tsu(D)IOR ta(A)IO td(CLKH-ISTRBL) td(CLKL-A) ta(ISTRBL)IO th(ISTRBH-D)R Figure 6--6. Parallel I/O Port Read |
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