TNETV1002IDZHK datasheet(90/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.15 ARM Clock Timings

The ARM SRAM timings are derived from the ARM clock. The clock switching characteristics are defined in

Table 6--35 for use in the ARM SRAM timing definitions.

Table 6--35. ARM SRAM Switching Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

tc(ARM)

Cycle time, ARM clock

21.05

tw(ARM--H)

Pulse duration, ARM clock high

A/2 -- 3†

A/2†

A/2 + 3†

tw(ARM--L)

Pulse duration, ARM clock low

A/2 -- 3†

A/2†

A/2 + 3†

tw(ARM--W)

Pulse duration, ARM write cycle

A/2 + nA†‡

tw(ARM--R)

Pulse duration, ARM read cycle

A+ nA†‡

† A= tc(ARM)

‡ n = the number of software wait states

The ARM SRAM write timing requirements listed in Table 6--36 represent back-to-back write operations to

a zero-wait-state SRAM device.

Table 6--36 through Table 6--37 assume testing over recommended operating conditions (see Figure 6--35

and Figure 6--36).

Table 6--36. ARM SRAM Timing Requirements (Write)

MIN

NOM

MAX

UNIT

td(CSL-AV)

Delay time, address valid from CS low

-- 3

td(CSL-DV)

Delay time, data valid from CS low

--2

td(CSL-WEL)

Delay time, write enable low from CS low

tw(WEL)

Pulse width, write enable low

D-- 3.5§

D§

D+ 3.5§

td(WEH--AIV)

Delay time, address invalid from write enable high

td(WEH--DIV)

Delay time, data invalid from write enable high

td(WEH--DV)

Delay time, data valid from write enable high

tw(WEH)

Pulse width, write enable high

A/2 -- 3.5†

A/2†

A/2 + 3.5†

td(WEH--CSH)

Delay time, CS high from write enable high

10 td(CSL--BEV)

Delay time, byte enable valid from CS low

-- 3

11 td(WEH--BEIV)

Delay time, byte enable invalid from write enable high

12 td(WEH--BEV)

Delay time, byte enable valid from write enable high

20 td(CSL-OEH)

Delay time, output enable high from CS low

-- 3

21 td(WEH--OEL)

Delay time, output enable low from write enable high

† A= tc(ARM)

§ D= tw(ARM-W)

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