TNETV1002IDZHK datasheet(44/102 Pages) TI1

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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

Movement of data between the FIFOs and the packet memory is directed via a data structure in the packet

memory called the descriptor rings (DR). In general, the DR data structures provide flexible packet

management allowing variable memory buffer sizes and locations. The DR also provides a means to

synchronize shared ownership of data buffers in memory between the Ethernet interface and the MCU. Each

ring consists of a variable number of descriptors which can be chained to handle long packets in multiple data

buffer areas. The location of the descriptor rings in memory is programmable using Ethernet interface

configuration registers. One descriptor ring is for transmit operations and the other is for receive operations.

The packet memory provides two circular queues for Ethernet packets: one queue for received packets and

one queue for transmit packets for the port (ENET0). Each queue is a list of descriptors which includes control

and status information, and a pointer to packet data. When the MCU software identifies a packet which must

be moved from one queue to another, only the descriptors (pointing to the packet data) are copied, i.e., data

packet is passed by reference. Each descriptor is linked to a packet buffer. To keep track of free buffers, a

free buffer entry is added after each packet buffer. This allows a buffer to be referenced by two descriptors

of two different queues, which is useful when receiving broadcast or multicast packets.

The Ethernet interface accesses each descriptor circular queue in strict sequential fashion. If the Ethernet

interface wants to process a descriptor entry to transmit a packet, it will check the ownership bit. If the MCU

owns the entry, the controller will periodically poll the entry waiting for ownership to be passed to the ENET

module. If ownership is not passed before the buffer empties, a transmit underflow will occur. Likewise, for

receive operations, the controller will poll and wait for the next descriptor entry to become available. If

ownership is not passed before the buffer fills, a receive overflow will occur. The user may set the poll time

by loading the 16-bit poll interval register, which defines the number of MCU subsystem clocks between polls.

The Ethernet interface does not check the length of a chained descriptor. MCU software should avoid creating

linked descriptors that violate Ethernet rules.

It is the responsibility of MCU software to initialize the packet memory structure and circular queues, and to

ensure coherence with the configuration values programmed in the Ethernet interface registers.

4.3.1.1

EIM Operation

The MCU software has the responsibility to initialize the Ethernet interface module (EIM).

•

Packet buffer memory initialization

The MCU software has to initialize the descriptor rings structures. It is a requirement that each

descriptor points to an existing buffer and that each buffer is only referenced once. Interrupts have to

be enabled on all descriptors. All descriptors have to be owned by their own port (OWN=1). Buffer

usage entries have to be initialized to zero.

•

ENET0 initialization

If the ENET module is not used it could be disabled by clearing permanently the ENABLE bit of the

MODE register.

The mode, backoff seed, backoff count, TX flow go, flow control, VTYPE, ring poll interval registers

have to be set according to the operating configuration.

The TDBA and RDBA registers have to be set according to the mapping done in the packets memory.

The logical address hash filter register has to be initialized to zero.

The ENET has to be set in all pass mode in the address mode enable register. If MCU logical

addressing is desired, the enable logical address bit has to be set to one as well.

•

EIM start-up

The ENET has to be started by setting the ENABLE bit in its MODE register.

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