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TNETV1002IDZHK 数据表(PDF) 24 Page - Texas Instruments

部件名 TNETV1002IDZHK
功能描述  Fixed-Point Digital Signal Processor
PDF  102 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV1002IDZHK 数据表(HTML) 24 Page - Texas Instruments

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DSP Subsystem Functional Overview
14
June 2001 -- Revised December 2002
SPRS180C
Hex
Page 0 Program,
MP/MC =1
(Microprocessor Mode)
Hex
Page 0 Program,
MP/MC =0
(Microcomputer Mode)
Hex
Data
0000
OVLY = 1
OVLY = 0
0000
OVLY = 1
OVLY = 0
0000
007F
Reserved
External
Program
Space
Memory
007F
Reserved
External
Program
Space
Memory
007F
Memory Mapped Registers,
Scratch-Pad RAM
0080
On-chip Data
DARAM
External
Program
Space
0080
On-chip Data
DARAM
External
Program
Space
0080
On-chip Data DARAM
(8K--0x80 Words)
1FFF
DARAM
Space
Memory
1FFF
DARAM
Space
Memory
1FFF
(8K--0x80 Words)
2000
On-chip Data
DARAM API
External
Program
2000
On-chip Data
DARAM API
External
Program
2000
On-chip Data DARAM,
API Accessible
3FFF
DARAM, API
accessible
Program
Space
Memory
3FFF
DARAM, API
accessible
Program
Space
Memory
3FFF
API Accessible
(8K Words)
4000
On-chip Data
External
Program
4000
On-chip Data
External
Program
4000
On-chip Data SARAM
5FFF
On chip Data
SARAM
Program
Space
Memory
5FFF
On chip Data
SARAM
Program
Space
Memory
5FFF
On chip Data SARAM
(8K Words)
6000
External Program Space
Memory
6000
On-chip Program SARAM
(8K words program only)
6000
On-chip Data SARAM,
(8K Words data only)
7FFF
Memory
7FFF
(8K words, program only)
7FFF
(8K Words, data only)
8000
8000
On-chip Program SARAM
8000
9FFF
On-chip Program SARAM
(8K words, program only)
E ter al Data Space Me or
A000
On-chip Program SARAM
External Data Space Memory
External Program Space
BFFF
On-chip Program SARAM
(8K words, program only)
BFFF
External Program Space
Memory
C000
On-chip Program SARAM
C000
DROM=1
DROM=0
y
DFFF
On chip Program SARAM
(8K Words)
On-Chip
External
E000
On-chip Program SARAM
On-Chip
Program
SARAM
External
Data-space
Memory
FFFF
FFFF
On chip Program SARAM
(8K words)
FFFF
SARAM
Memory
Figure 3--2. Memory Map for DSP Accesses (DSP_APIBN = 1 or ABMDIS = 1)
3.2.3 API Boot Mode
Under normal DSP subsystem reset conditions, the DSP will begin operation either from code that has been
previously uploaded to internal program-space RAM (when in microcontroller mode) or from external memory
on the XIO bus (microprocessor mode). Uploading the code to internal program-space RAM may be
performed by the MCU. When the DSP subsystem is in API boot mode, the upper 2K words of the 8K-word
API SARAM is shadowed so that it is found both in DSP data space at 0x3800--0x3FFF and in DSP program
space at 0xF800 to 0xFFFF, which includes the DSP’s reset vector.
To make use of this mode, the MCU directly controls the DSP’s reset and API boot mode signals. It holds the
DSP in reset, enables API boot mode, and loads the DSP boot code via the API. Once it has loaded the code
to the appropriate location in the API SARAM, the MCU releases the DSP from reset, and the DSP begins
executing from the normal reset location, where the uploaded code now resides. Once the DSP code has
completed any API boot activity, it may disable the memory remapping provided by the API boot mode by
writing a 1 to BSCR[4] (ABMDIS). It is recommended that the MCU change the API boot mode input signal
only when the DSP is held in reset.



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