 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TNETV1002IDZHK 数据表(PDF) 26 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TNETV1002IDZHK 数据表(HTML) 26 Page - Texas Instruments |
|
|
26 / 102 page  DSP Subsystem Functional Overview 16 June 2001 -- Revised December 2002 SPRS180C 3.2.5 DSP Extended Program Memory The DSP subsystem includes a memory paging scheme to extend the number of addressable program space locations from 64K to 1M words. The four extended address pins (DSP_A16 to DSP_A19) are used to address 15 pages of program memory. Each page includes 64K addressable locations. The extended program addresses are supported by eight instructions: FB[D], FBACC[D], FCALA[D], FCALL[D], FRET[D], FRETE[D], READA, and WRITA. • FB[D] – Far branch • FBACC[D] – Far branch to the location specified by the value in accumulator A or accumulator B • FCALA[D] – Far call to the location specified by the value in accumulator A or accumulator B • FCALL[D] – Far call • FRET[D] – Far return • FRETE[D] – Far return with interrupts enabled • READA – Read program memory addressed by accumulator A and store in data memory • WRITA – Write data to program memory addressed by accumulator A For more information on these instructions, please refer to the TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set (literature number SPRU172). When the OVLY bit is set, each page of program memory is made up of two parts: a common block of 24K words maximum and a unique block of 40K words minimum. The common block is shared by all pages, and each unique block is accessible only through its assigned page. The value of the program counter extension register (XPC) defines the page selection. At a hardware reset, the XPC is initialized to 0. 0 0000 1 0000 1 5FFF Page 1 Lower 24K† External 2 0000 2 5FFF Page 2 Lower 24K† External ... ... F 0000 F 5FFF Page 15 Lower 24K† External Page 0 1 6000 2 6000 F 6000 g 64K Page 1 Upper 40K External Page 2 Upper 40K External ... ... Page 15 Upper 40K External 0 FFFF 1 FFFF 2 FFFF F FFFF † Accesses to the lower 24K words of pages 1 through 15 are to external program memory only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, on-chip RAM is mapped to 0x0 to 0x5FFF of pages 1 through 15. Note external address pins are provided to support 15 external pages. Figure 3--4. DSP Extended Program Memory Map 3.2.6 DSP Relocatable Interrupt Vector Table The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
