TNETV1002IDZHK datasheet(92/102 Pages) TI1

92 / 102 page

Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

The ARM SRAM read timing requirements listed in Table 6--37 represent back-to-back read operations to a

zero-wait-state SRAM device.

Table 6--37. ARM SRAM Timing Requirements (Read)

MIN

MAX

UNIT

td(CSL-AV)

Delay time, address valid from CS low

-- 3

td(CSL--BHEV1)

Delay time, byte enable high valid 1 from CS low

-- 3

td(CSL-OEL)

Delay time, output enable low from CS low

-- 3

td(CSL-AIV1)

Delay time, address invalid 1 from CS low

E-- 3†

E+ 4†

tw(CSL)

Pulse duration, CS low

2E -- 3.5†

2E + 3.5†

tsu(CSL-DV1)

Setuptime, datavalid1fromCS low

E-- 12†

td(CSL--AIV2)

Delay time, address invalid 2 from CS low

2E -- 3†

2E + 4†

th(CSL--DIV1)

Hold time, data invalid 1 from CS low

E-- 1†

tsu(CSL--DV2)

Setuptime, datavalid2fromCS low

2E -- 12†

10 td(CSL--BEIV1)

Delay time, byte enable invalid 1 from CS low

E-- 4†

E+ 4†

11 td(CSL--BEV2)

Delay time, byte enable valid 2 from CS low

E-- 2†

E+ 6†

12 th(CSL--DIV2)

Hold time, data invalid 2 from CS low

2E -- 1†

13 td(CSL--BEIV2)

Delay time, byte enable invalid 2 from CS low

2E -- 4†

2E + 4†

14 td(CSL--OEH)

Delay time, output enable high from CS low

2E -- 3†

2E + 4†

† E= tw(ARM--R)

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