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TNETV1002IDZHK 数据表(PDF) 91 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 91 Page - Texas Instruments |
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91 / 102 page ![]() Electrical Specifications 81 June 2001 -- Revised December 2002 SPRS180C B 1 5 5 2 6 7 6 3 4 8 4 9 10 12 11 11 20 21 ARM_MCLK ADD[22:0] DATA[31:0] R/W CSn BE[3:0] OE D‡ C D† A † n=0wait states ‡ n=1or morewait states NOTE: When performing a 32-bit access on a 16-bit-wide SRAM, two of the byte-enables will be active at the same time. The particular byte-enables active depend on the endiannism selected. Figure 6--35. ARM SRAM Write Timing |
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