TNETV1002IDZHK datasheet(78/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.11.3

McBSP as SPI Master or Slave Timings

Low inactive state without delay; the McBSP transmits data on the rising edge of BCLKX and receives data

on the falling edge of BCLKR.

Table 6--20 and Table 6--21 assume testing over recommended operating conditions, CLKSTP = 10b,

CLKXP = 0, and H = 0.5tc(CO) (see Figure 6--19).

NOTE: For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting

CLKSM = CLKGDV = 1.

Table 6--20. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b and CLKXP = 0)

MASTER

SLAVE

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(BDRV-BCKXL)

Setup time, BDR valid before BCLKX low

-- 12H

th(BCKXL-BDRV)

Hold time, BDR valid after BCLKX low

12H + 5

tsu(BFXL-BCKXH)

Setup time, BFSX low before BCLKX high

tc(BCKX)

Cycle time, BCLKX

12H

32H

Table 6--21. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b and CLKXP = 0)

PARAMETER

MASTER†

SLAVE

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

th(BCKXL-BFXL)

Hold time, BFSX low after BCLKX low‡

T-- 6

T+6

td(BFXL-BCKXH)

Delay time, BFSX low to BCLKX high§

C-- 6

C+ 6

td(BCKXH-BDXV)

Delay time, BCLKX high to BDX valid

-- 3

6H + 5 10H + 14

tdis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BCLKX low

C-- 2

C+ 3

tdis(BFXH-BDXHZ)

Disable time, BDX high impedance following last data bit from BFSX

high

2H+ 3

6H + 17

td(BFXL-BDXV)

Delay time, BFSX low to BDX valid

4H + 2

8H + 17

† T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

‡ FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

§ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

BCLKX

BFSX

BDX

BDR

tsu(BDRV-BCLXL)

td(BCKXH-BDXV)

th(BCKXL-BDRV)

tdis(BFXH-BDXHZ)

tdis(BCKXL-BDXHZ)

th(BCKXL-BFXL)

td(BFXL-BDXV)

td(BFXL-BCKXH)

LSB

MSB

tsu(BFXL-BCKXH)

tc(BCKX)

Figure 6--19. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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