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数据搜索系统，热门电子元器件搜索 |
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TNETV1002IDZHK 数据表(PDF) 31 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 31 Page - Texas Instruments |
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31 / 102 page  DSP Subsystem Functional Overview 21 June 2001 -- Revised December 2002 SPRS180C Table 3--5. Relationship Between BNKCMP and Bank Size BNKCMP MSB TO COMPARE BANK SIZE Bit 15 Bit 14 Bit 13 Bit 12 MSBs TO COMPARE (16-BIT WORDS) 0 0 0 0 None 64K 1 000 15 32K 1 1 0 0 15--14 16K 1 1 1 0 15--13 8K 1 1 1 1 15--12 4K The external memory interface can be disabled when not used. This feature can be used to reduce the power consumption of the 5471 DSP subsystem. Table 3--6 lists the states of the external interface pins, when the interface is disabled (EXIO=1). Table 3--6. State of Signals When External Bus Interface is Disabled (EXIO = 1) SIGNAL STATE SIGNAL STATE DSP_A(19--0) Previous State DSP_MSTRB High Level DSP_D(15--0) High Impedance DSP_IOSTRB High Level DSP_PS High Level DSP_R/W High Level DSP_DS High Level KBGPIO12/DSP_MSC† High Level DSP_IS High Level KBGPIO11/DSP_IAQz‡ High Level † Only applies when KBGPIO12 is enabled to output DSP_MSC. ‡ Only applies when KBGPIO11 is enabled to output DSP_IAQ 3.3.3 Processor Mode Status Register The 5471 DSP subsystem processor mode status register (PMST) differs from the typical C54x design in that the PMST CLKOUT bit has no effect on the CLKOUT port of the subsystem. This port is always clocking when the DSP subsystem’s PLL is active. |
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