TNETV1002IDZHK datasheet(67/102 Pages) TI1

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Electrical Specifications

June 2001 -- Revised December 2002

SPRS180C

6.6.4 Parallel I/O Port Write Switching Characteristics

Table 6--11 assumes testing over recommended operating conditions with DSP_IOSTRB = 0 and

H = 0.5tc(CO) (see Figure 6--7).

Table 6--11. Parallel I/O Port Write Switching Characteristics†

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, DSP_CLKOUT low to address valid

1.5

11.5

td(CLKH-ISTRBL)

Delay time, DSP_CLKOUT high to DSP_IOSTRB low

1.5

11.5

td(CLKH-D)IOW

Delay time, DSP_CLKOUT high to write data valid

1.5

11.5

td(CLKH-ISTRBH)

Delay time, DSP_CLKOUT high to DSP_IOSTRB high

1.5

11.5

td(CLKL-RWL)

Delay time, DSP_CLKOUT low to DSP_R/W low

1.5

11.5

td(CLKL-RWH)

Delay time, DSP_CLKOUT low to DSP_R/W high

1.5

11.5

th(A)IOW

Hold time, address valid after DSP_CLKOUT low

1.5

11.5

th(D)IOW

Hold time, write data after DSP_IOSTRB high

H--3

H+3

tsu(D)DSP_IOSTRBH Setup time, write data before DSP_IOSTRB high

H--3

H+3

tsu(A)DSP_IOSTRBL Setup time, address valid before DSP_IOSTRB low

H--3

H+3

† Address and DSP_IS timings are included in timings referenced as address.

DSP_IS

DSP_R/W

DSP_IOSTRB

DSP_D[15:0]

DSP_A[19:0]

DSP_CLKOUT

td(CLKH-ISTRBH)

th(A)IOW

th(D)IOW

td(CLKH-D)IOW

td(CLKH-ISTRBL)

td(CLKL-A)

td(CLKL-RWL)

td(CLKL-RWH)

tsu(A)DSP_IOSTRBL

tsu(D)DSP_IOSTRBH

Figure 6--7. Parallel I/O Port Write

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