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TNETV1002IDZHK 数据表(PDF) 74 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 74 Page - Texas Instruments |
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74 / 102 page  Electrical Specifications 64 June 2001 -- Revised December 2002 SPRS180C 6.11 Multichannel Buffered Serial Port (McBSP) Timings 6.11.1 McBSP Receive and Transmit Timings Table 6--16 and Table 6--17 assume testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6--16 and Figure 6--17). NOTE: Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. Table 6--16. McBSP Receive and Transmit Timing Requirements MIN MAX UNIT tc(BCKRX) Cycle time, BCLK_R/X BCLK_R/X ext 4H ns tw(BCKRX) Pulse duration, BCLK_R/X or BCLK_R/X high BCLK_R/X ext 2H--1 ns t H ld ti t l BFSR hi h ft BCLKR l BCLKR int 0 th(BCKRL-BFRH) Hold time, external BFSR high after BCLKR low BCLKR ext 7 ns t H ld ti BDR lid ft BCLKR l BCLKR int 0 th(BCKRL-BDRV) Hold time, BDR valid after BCLKR low BCLKR ext 7 ns t H ld ti t l BFSX hi h ft BCLKX l BCLKX int 0 th(BCKXL-BFXH) Hold time, external BFSX high after BCLKX low BCLKX ext 7 ns t S t ti t l BFSR hi h b f BCLKR l BCLKR int 9 tsu(BFRH-BCKRL) Setup time, external BFSR high before BCLKR low BCLKR ext 2 ns t S t ti BDR lid b f BCLKR l BCLKR int 9 tsu(BDRV-BCKRL) Setup time, BDR valid before BCLKR low BCLKR ext 2 ns t S t ti t l BFSX hi h b f BCLKX l BCLKX int 9 tsu(BFXH-BCKXL) Setup time, external BFSX high before BCLKX low BCLKX ext 2 ns tr(BCKRX) Rise time, BCLKR_R/X BCLK_R/X ext 5 ns tf(BCKRX) Fall time, BCLKR_R/X BCLK_R/X ext 5 ns |
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