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TNETV1002IDZHK 数据表(PDF) 27 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 27 Page - Texas Instruments |
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27 / 102 page ![]() DSP Subsystem Functional Overview 17 June 2001 -- Revised December 2002 SPRS180C At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page. NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space. 3.3 DSP Registers The 5471 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h to 1Fh. Table 3--1 gives a list of CPU memory-mapped registers (MMRs) available on 5471. The device also has a set of memory-mapped registers associated with peripherals as shown in Table 3--2. Table 3--1. CPU Memory-Mapped Registers NAME ADDRESS DESCRIPTION NAME DEC HEX DESCRIPTION IMR 0 0 Interrupt mask register IFR 1 1 Interrupt flag register – 2--5 2--5 Reserved for testing ST0 6 6 Status register 0 ST1 7 7 Status register 1 AL 8 8 Accumulator A low word (15--0) AH 9 9 Accumulator A high word (31--16) AG 10 A Accumulator A guard bits (39--32) BL 11 B Accumulator B low word (15--0) BH 12 C Accumulator B high word (31--16) BG 13 D Accumulator B guard bits (39--32) TREG 14 E Temporary register TRN 15 F Transition register AR0 16 10 Auxiliary register 0 AR1 17 11 Auxiliary register 1 AR2 18 12 Auxiliary register 2 AR3 19 13 Auxiliary register 3 AR4 20 14 Auxiliary register 4 AR5 21 15 Auxiliary register 5 AR6 22 16 Auxiliary register 6 AR7 23 17 Auxiliary register 7 SP 24 18 Stack pointer register BK 25 19 Circular buffer size register BRC 26 1A Block repeat counter RSA 27 1B Block repeat start address REA 28 1C Block repeat end address PMST 29 1D Processor mode status (PMST) register XPC 30 1E Extended program page register – 31 1F Reserved |
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