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TNETV1002IDZHK 数据表(PDF) 94 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 94 Page - Texas Instruments |
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94 / 102 page  Electrical Specifications 84 June 2001 -- Revised December 2002 SPRS180C 6.16 SPI Clock Timings SPI timings are derived from the internal SPI clock. This clock is only available externally during a serial transfer. Table 6--38 through Table 6--40 assume testing over recommended operating conditions (see Figure 6--37 and Figure 6--38). Table 6--38. SPI Clock Switching Characteristics PARAMETER MIN TYP MAX UNIT tc(SPI) Cycle time, CLKX_SPI 168.4 A† ns tw(SPI--H) Pulse duration, CLKX_SPI high A/2 -- 3† A/2† A/2 + 3† ns tw(SPI--L) Pulse duration, CLKX_SPI low A/2 -- 3† A/2† A/2 + 3† ns tr(SPI) Rise time, SPI output signals. CLKX_SPI, MCUDO, MCUEN0, MCUEN1, and MCUEN2 1 4 ns tf(SPI) Fall time, SPI output signals. CLKX_SPI, MCUDO, MCUEN0, MCUEN1, and MCUEN2 1 4 ns † A= 4 x PTVx tc(ARM) Table 6--39. SPI Falling Edge Timing Requirements MIN NOM MAX UNIT td(ENFS--CLKH) Delay time, Falling enable start active to first clock high A/2 -- 3† A/2† A/2 + 3† ns td(CLKL--ENFE) Delay time, Last clock low to falling enable end A-- 3† A† A+ 3† ns tw(ENFT) Pulse duration, Falling enable toggle A-- 3† A† A+ 3† ns td(CLKH--DOV) Delay time, Clock high to data out valid 2 8 ns tsu(DIV--CLKL) Setup time, Data in valid to clock low 6 ns th(CLKL--DIIV) Hold time, Clock low to data in invalid 4 ns † A= 4 x PTVx tc(ARM) In this mode, all timing related activity for Data In and Enable is based on the falling edge of the SPI Clock. The timing activity for Data Out will be based on the rising edge of the SPI clock. |
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