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DSP Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

Table 3--4. Bank-Switching Control Register (BSCR) Bit Fields

BIT

RESET

FUNCTION

NO.

NAME

RESET

VALUE

FUNCTION

15--12

BNKCMP

1111

Bank compare. Determines the external bank size. BNKCMP is used to mask the four MSBs of an address.

For example, if BNKCMP = 1111b, the four MSBs (bits 15--12) are compared, resulting in a bank size of

4K words. Bank sizes of 4K words to 64K words are allowed. Table 3--5 shows the relationship between

BNKCMP and the address range.

PS--DS

Program read -- data read access. Inserts an extra cycle between consecutive accesses of program read

and data read, or data read and program read.

PS--DS = 0: No extra cycles are inserted by this feature

PS--DS = 1: One extra cycle is inserted between consecutive data and program reads.

10--5

Reserved

These bits are reserved and will retain written values.

ABMDIS

API boot mode disable. This bit will force the DSP out of API boot mode. This bit has no effect when the

DSP_APIBN is high. When DSP_APIBN is low, a 0 in this bit enables API boot mode anda1disables API

boot mode. Note that a DSP subsystem reset will clear this bit and thus re-enable the DSP_APIBN port.

ABMDIS = 0: API boot mode is under the control of DSP_APIBN

ABMDIS = 1: DSP_APIBN is ignored and DSP subsystem is kept out of API boot mode

HINT

Host processor interrupt. This bit enables/disables an interrupt to the MCU from the DSP. At reset, the HINT

bit is cleared. To send a proper interrupt to the MCU, the DSP must writea1toHINT, delay an appropriate

time, then writea0toHINT tocreateapulse of an appropriate duration on the interrupt signal to the MCU.

HINT = 0: Interrupt signal to the MCU is not active

HINT = 1: Interrupt signal to the MCU is active

APIMODE

HOM/SAM enable. This bit enables/disables the API host-only mode.

APIMODE = 0: The shared-access mode (SAM) is enabled. Both the DSP and the MCU may access

the API RAM.

APIMODE = 1: The host-only mode (HOM) is enabled. The MCU may access the API RAM; the DSP

may not access the API RAM. DSP writes to the API RAM are ignored, and DSP reads from the API

RAM return undefined values. DSP IDLE modes have no effect on MCU accesses to the API memory

when in host-only mode.

Reserved

These bits are reserved and will retain written values.

EXIO

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0: The external bus interface functions as usual.

EXIO = 1: The address bus, data bus, and control signals become inactive after completing the current

bus cycle. Table 3--6 lists the states of the external interface signals when the interface is disabled.

Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1 cannot be modified

when the interface is disabled.

3.3.2 Programmable Bank-Switching Wait-States

The bank-switching features of the programmable bank-switching logic of the 5471 DSP subsystem is

functionally equivalent to that of the 5409. This feature automatically inserts one cycle when accessing across

memory-bank boundaries within program or data memory space. A bank-switching wait-state can also be

automatically inserted when accessing across the data space to program space boundary. These features

are programmed via the BNKCMP and PS--DS bits in the BSCR.

The relationship between BNKCMP, the address bits to be compared, and the bank size is summarized in

Table 3--5. The BNKCMP values that are not listed in the table are not allowed.

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