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TNETV1002IDZHK 数据表(PDF) 34 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 34 Page - Texas Instruments |
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34 / 102 page  DSP Subsystem Functional Overview 24 June 2001 -- Revised December 2002 SPRS180C 3.4.2.5 DMA controller synchronization events The internal transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in Table 3--9. Table 3--9. DMA Synchronization Events DSYN VALUE DMA SYNCHRONIZATION EVENT 0000b No synchronization used 0001b McBSP0 receive event 0010b McBSP0 transmit event 0011b Reserved 0100b Reserved 0101b McBSP1 receive event 0110b McBSP1 transmit event 0111b Reserved 1000b Reserved 1001b Reserved 1010b Reserved 1011b Reserved 1100b Reserved 1101b Timer interrupt event 1110b External interrupt 0 1111b Reserved 3.4.2.6 DSP DMA Channel Interrupt Selection The DMA controller can generate a DSP interrupt for each of the six channels. However, due to a limit on the number of internal DSP interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When the DSP is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in Table 3--10. Table 3--10. DMA Channel Interrupt Selection INTSEL Value IMR/IFR[6] IMR/IFR[7] IMR/IFR[10] IMR/IFR[11] 00b (reset) Reserved Reserved BRINT1 BXINT1 01b Reserved Reserved DMAC2 DMAC3 10b DMAC0 DMAC1 DMAC2 DMAC3 11b Reserved 3.4.3 ARM Port Interface (API) Information is exchanged between the MCU and the DSP through the on-chip shared API memory. The API memory is a 8K × 16-bit word DARAM (dual-access RAM) block. The API memory can also be used by the DSP as general-purpose data or program DARAM. In this circuit, only the DSP memory has DARAM. The API has two modes of operation selected by the bank switching control register (BSCR): shared-access mode (SAM) and host-only mode (HOM). In SAM, both the DSP and the MCU can access the API memory. In SAM, asynchronous host accesses from the MCU are resynchronized internally. If the DSP and the MCU try to perform an access at the same time, the MCU has access priority and the DSP waits one cycle. SAM can be run when the DSP is in IDLE1 mode. In HOM, only the MCU can access the API memory. When HOM is selected, API memory blocks are disabled for DSP access, no value can be read from nor written to those memory locations. |
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