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TNETV1002IDZHK 数据表(PDF) 71 Page - Texas Instruments |
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TNETV1002IDZHK 数据表(HTML) 71 Page - Texas Instruments |
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71 / 102 page  Electrical Specifications 61 June 2001 -- Revised December 2002 SPRS180C 6.8 Interrupt Timings Table 6--13 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 6--12). Table 6--13. Reset and Interrupt Timing Requirements MIN MAX UNIT tw(INTH)S Pulse duration, DSP_INT0 high (synchronous) 2H+1 ns tw(INTL)S Pulse duration, DSP_INT0 low (synchronous) 2H+1 ns tw(INTL)A Pulse duration, DSP_INT0 low (asynchronous) 4H ns tw(INTL)WKP Pulse duration, DSP_INT0 low for IDLE2/IDLE3 wakeup 10 ns tsu(INT) Setup time, DSP_INT0 before DSP_CLKOUT low† 8 10 ns † The external interrupt is synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs with consecutive falling edges of DSP_CLKOUT. The input to the interrupt pin is required to represent a 1-0-0 sequence at the timing that is corresponding to three DSP_CLKOUT sampling sequences. DSP_INT0 DSP_CLKOUT th(INT) tsu(INT) tsu(INT) tw(INTL)A tw(INTH)A Figure 6--12. Interrupt Timing |
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