PC87570-ICCSLASHVUL datasheet(121/168 Pages) NSC

121 / 168 page

Analog to Digital Converter (ADC) - January 1998

121

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Note: After the ADC is enabled, it is recommended not to

change the control bits listed in Table 16-1 on page 120.

Otherwise, unpredictable results may occur.

16.2.6

ADC Operation

Before starting the conversion, the ADC should be initial-

ized and enabled as described in Section 16.2.5. Then fol-

low the procedures listed in Table 16-2.

Either a single conversion or a burst of four conversions

may be selected, to be executed once or continuously. The

conversion parameters are defined by fields in the

ADCCNT1 and ADCCNT2 Registers. See Section 16.3 for

more details. A conversion is started when the START bit of

the ADCCNT2 Register is set. All ADCCNT2 fields may be

written simultaneously in a single register access, as shown

in Table 16-2. In continuous conversion modes, repeat the

last two steps for as long as samples are needed. Then,

stop the ADC by clearing START.

Table 16-2. Procedure for ADC Operation

16.2.7

Disabling the ADC to Save Power

When the ADC is not converting, it may be disabled to re-

duce its current consumption from the AVCC to less than

0.1

µA. The PC87570 must first be placed in Idle mode, as

described in Section 8.3.1.

The decision to disable the ADC should be based on the ex-

pected Idle mode period, as follows:

If shorter than 100

µs, the ADC should remain en-

abled.

If longer than 100

µs and if an additional latency peri-

od of 100

µs is acceptable when returning from Idle

mode, the ADC can be disabled to save power.

See Figure 16-3 for the correct sequence for disabling it.

First make sure that the START bit of the ADCCNT2 Regis-

ter is cleared. Then check the BUSY bit of the ADCST Reg-

ister; if set, wait until it is cleared by the hardware before

disabling the ADC.

16.2.8

Sampling Time

The sampling time begins from when the START bit of the

ADCCNT2 Register is set until the conversion starts. The

DELAY bit of the ADCCNT3 Register defines this time, ei-

ther from when START is set or from completion of a previ-

ous conversion. During this time, the sampling capacitor is

charged. To allow flexibility, the sampling time is program-

mable by delaying the ADC conversion start until the signal

on the Sample and Hold capacitor settles.

Each conversion operation takes 10 ADC clock cycles. To

calculate the sampling time, see Table 9-1 on page 81.

16.2.9

Polling Driven Operation

Results may be read by polling EOC of the ADCST Regis-

ter. When this bit is set, a valid result is held in the data buff-

ers. Registers ADDATA0-3 hold results according to the

ADC operation mode. BUFPTR of the ADCST Register

points to the last data item written to the buffer. EOC is

cleared by reading the results.

16.2.10 Interrupt Driven Operation

The ADC can generate an interrupt to the CR16A core upon

completion of a conversion. The interrupt is routed to the

ICU, as INT5. See Table 9-2 on page 82.

To enable interrupt generation from the ADC interface to the

ICU, INTE of the ADCCNT1 Register must be set. The ADC

then issues an interrupt when EOC of the ADCST Register is

set. The interrupt request type is high level, and is asserted

when the buffer is full or when the operation is completed, ac-

cording to the specific operation mode. The interrupt request

is deasserted when any one of the data registers is read.

16.2.11 Overflow

An overflow occurs when a conversion is completed and its

designated data buffer is full. A data buffer is full if it con-

tains valid data and is not read until new data is ready.

If an overflow occurs, the new data overrides the old data in

the buffer, and OVF of the ADCST Register is set.

Once set by an overflow condition, OVF remains set until

the software clears it by writing 1 to it.

Action

Description

1. Set ADCEN=1

ADCCNT1

Enable the ADC

2. Set CHANNEL,

CONT and SCAN

ADCCNT2

Select channel and

mode

3. Set START=1

ADCCNT2

Start conversion

4. Wait until EOC=1

ADCST

Poll until end of

conversion, or use

interrupt

5. Read ADDATA0-3 ADDATA0-3 Read

conversion

results

Is START

set?

Clear START

Wait

Clear ADCEN

Yes

Figure 16-3. Disabling ADC Sequence

Is BUSY

set?

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