PC87570-ICCSLASHVUL datasheet(118/168 Pages) NSC

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Timer and WATCHDOG (TWD)

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Bits 2-0 - Main Clock Divide (MDIV)

Defines the pre-scale ratio of the input clock. The pre-scale

ratio is 2MDIV. MDIV must be in the range of zero to five, pro-

viding a pre-scale ratio of 1 to 32. Table Figure 15-1 sum-

marizes MDIV allowed values.

Table 15-1. MDIV Values

15.6.3

TWD Timer 0 Register (TWDT0)

The TWDT0 Register is a read/write register. It defines the

T0OUT interrupt rate. Upon reset, this register is initialized

to FFFFh.

Bits 7-0 - PRESET

Defines the counter preset value. Whenever the counter

reaches zero, it starts counting down from this value.

The T0OUT frequency is the T0IN frequency divided by

(PRESET+1). The allowed values of the PRESET field

are 0001h through FFFFh.

15.6.4

TWDT0 Control and Status Register (T0CSR)

The T0CSR Register is a read/write register. It controls the

operation and provides the status of the T0 timer. The non-

reserved bits of T0CSR are cleared (0) on reset.

Bit 0 - Restart (RST)

When set (1), forces the timer to restart counting in the

next input clock rising edge. The bit is cleared by the in-

put clock rising edge, indicating that the counter re-

sumed its automatic re-triggerable operation. Writing 0

to this bit is ignored.

Bit 1 - Terminal Count (TC)

The TC bit indicates that the counter has reached zero (ter-

minal count). This bit is cleared each time the register is

read. It is a read only bit and data written to it is ignored.

15.6.5

WATCHDOG Count Register (WDCNT)

The WDCNT Register is a byte wide, write only register. It

holds the value loaded into the WATCHDOG counter when it

is serviced, and counts down from it. The WATCHDOG is

started by the first write to the register. Each successive write

restarts the WATCHDOG count. Upon reset this register is ini-

tialized to 0Fh.

Bits 7-0 - PRESET

Defines the counter preset value. Whenever the counter

reaches zero, it starts counting down from this value.

The T0OUT frequency is the T0IN frequency divided by

(PRESET+1). The allowed values of the PRESET field

are 0001h through FFFFh.

15.6.6

WATCHDOG Service Data Match Register

(WDSDM)

The WDSDM Register is an 8-bit write only register. When

TWCFG.WDSDME is set, the WATCHDOG counting re-

starts from the value in WDCNT, when WDSDM is written

with 5Ch. If any other data is written to this register, it trig-

gers a WATCHDOG signal. If RSDATA is written for a sec-

ond time before one WATCHDOG clock has occurred, this

also triggers a WATCHDOG signal. Any write to this register

when TWCFG.WDSDME is cleared is ignored.

Bits 7-0 - Restart Data (RSDATA)

15.7 USAGE HINTS

The TWD protects WATCHDOG operation from software

tampering. To achieve the highest level of protection, pro-

ceed as follows:

1. Program the TWDT0 pre-scale and TMWT0 timers to

the desired values.

2. Configure the WATCHDOG clock to use T0IN or T0OUT

using TWCFG.WDCT0I bit.

3. Program the WDCTL to the maximum period between

WATCHDOG touch operations. Note that from this point,

the WATCHDOG starts operating and must be touched

periodically to prevent a WATCHDOG error signal.

4. Configure the WATCHDOG to use data match, and lock

all the TWD configuration and setting registers by set-

ting bits 0 through 4 and bit 6 of the WDCFG.

5. Touch the WATCHDOG by writing 5Ch to WDSDM at

the appropriate rate (i.e., no more than once every

WATCHDOG clock cycle and no less than the period

programmed to WDCTL).

MDIV

Clock Ratio

000

1:1

001

1:2

010

1:4

011

1:8

100

1:16

101

1:32

Other

Reserved

PRESET

Reserved

RST

PRESET

RSDATA

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