PC87570-ICCSLASHVUL datasheet(116/168 Pages) NSC

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Timer and WATCHDOG (TWD)

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15.0 Timer and WATCHDOG (TWD)

The TWD generates the clocks and interrupts used for tim-

ing periodic functions in the system; it also provides

WATCHDOG protection over software execution.

The TWD provides flexibility in system configuration by en-

abling the configuration of various clock ratios. After setting

the TWD configuration, the software can lock it to give a

higher level of protection against erroneous software action.

Once a section of the TWD is locked, only reset releases it.

15.1 FEATURES

• 32.768KHz input clock

• Programmable pre-scale counter

• 16-bit programmable periodic interrupt timer

• 8-bit WATCHDOG counter

• WATCHDOG signal generation in response to various

failure detection

15.2 FUNCTIONAL DESCRIPTION

15.2.1

Input Clock

The TWD bases all its counting activities on a 32.768KHz

clock. The WATCHDOG can count using a division of the

32KHz clock (either T0OUT or T0IN) or an alternate clock.

The alternate clock source is selected with a hardware se-

lection signal.

15.2.2

Pre-Scale

A pre-scale counter divides the input clock (32.768KHz) by

a factor of 2MDIV. MDIV (TWCP.MDIV field) is in the range

of 0 through 5 (i.e., divide ratio of 1:1 through 1:32). The

pre-scaled output is used as an input clock for a 16-bit timer

(TWDT0), and is referred to as T0IN.

15.2.3

TWD Timer 0

TWD Timer 0 is a 16-bit, programmable, automatically re-

triggered down-counter. It counts on the rising edge of

T0IN. It starts from the value loaded to TWDT0 register

down to zero, and then restarts counting from TWDT0 at the

next T0IN cycle.

When the counter reaches 0, T0OUT is set (1) for one T0IN

cycle. This makes the Timer 0 cycle:

TWDT0 + 1 x T0IN-cycle.

T0OUT is input to the ICU and can be used as the time base

for activities such as system tick.

When TWDT0 is loaded with a new value, the counter uses

it the next time it re-starts counting (i.e., after reaching ze-

ro). If timer control register T0CSR.RST is written 1, the tim-

er is restarted on the next rising edge of T0IN.

See Figure 15-1 for the TWD block diagram.

Note:

1. The T0CSR.RST bit is cleared after completing this

load.

2. When TWCP.MDIV=0, the timer counter may skip one

count when loaded with a new value.

(TWCP)

32.768KHz

16-Bit Timer

5-Bit Pre-Scale

Counter

WATCHDOG

Peripheral Bus

T0OUT

WATCHDOG

T0IN

FREEZ

TWDT0 Register

WDCNT

WDSDM

WATCHDOG

Service

Logic

Figure 15-1. Timer and WATCHDOG Block Diagram

Reset

from RTC

(in Dev Env only)

to ICU

TWCFG.WDCT0I

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