PC87570-ICCSLASHVUL datasheet(114/168 Pages) NSC

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Multi-Function 16-Bit Timer (MFT16)

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14.5 MFT16 REGISTERS

14.5.1

Clock Prescaler Register (TPRSC)

The TPRSC Register is a byte-wide read/write register. It

contains the current value of the clock prescaler, CLKPS.

The register is cleared on reset. It defines the timer clock

prescaler ratio.

Bits 4-0 - Clock Prescaler (CLKPS)

The timer clock is generated by dividing the system

clock by CLKPS+1. Therefore the maximum timer clock

frequency

equal

the

system

clock

(CLKPS=000002) and the minimum timer clock is the

system clock divided by 32 (CLKPS=111112).

14.5.2

Clock Unit Control Register (TCKC)

The TCKC Register is a byte-wide read/write register. It de-

fines the clock source selection for each timer counter. The

and timer/counter 2 clocks.

Bits 2-0 - Counter 1 Clock Select (C1CSEL)

Defines the clock mode for timer/counter 1 where:

000:

No Clock (Counter 1 stopped)

001:

Prescaled system clock

010:

External Event on TnB

011:

Pulse Accumulate

100:

Slow Speed Clock

Bits 5-3 - Counter 2 Clock Select (C2CSEL)

Defines the clock mode for timer/counter 2 where:

000:

No Clock (Counter 1 stopped)

001:

Prescaled system clock

010:

External Event on TnB

011:

Pulse Accumulate

100:

Slow Speed Clock

14.5.3

Timer/Counter Register 1 (TCNT1)

The TCNT1 Register is a word-wide register which is not al-

tered by reset. The value on power-on is unknown.

14.5.4

Timer/Counter Register 2 (TCNT2)

The TCNT2 Register is a word-wide read/write register which

is not altered by reset. The power-up value is unknown.

14.5.5

Reload/Capture Register A(TCRA)

The TCRA Register is a word-wide read/write register which

is not affected by reset and thus contains random data on

power-up.

14.5.6

Reload/Capture Register B (TCRB)

The TCRB Register is a word-wide read/write register which

is not affected by reset and thus contains random data on

power-up.

14.5.7

Timer Mode Control Register (TCTRL)

The TCTRL Register is a byte-wide read/write register. It

defines the mode of operation of the timer/counter and the

TA and TB I/O pins. The register is cleared on reset.

Bits 1-0 - Mode Select (MDSEL)

Defines the MFT16 mode of operation where:

00: Mode 1

01: Mode 2

10: Mode 3

11: Mode 4

Bit 2 - TA Edge Polarity (TAEDG)

When cleared (0) a high-to-low transition on TA causes

the action defined by the mode of operation e.g., input

capture. When set (1) a low-to-high transition on TA re-

sults in the defined action.

Bit 3 - TB Edge Polarity (TBEDG)

When cleared (0) a high-to-low transition on TB causes

the action defined by the mode of operation e.g., input

capture or external event count. When set (1) a low-to-

high transition on TB results in the defined action. In

pulse accumulate mode, when set (1) count is enabled

if TB is high. When cleared (0), and while operating in

pulse accumulate mode, the counter is enabled if TB is

low.

Reserved

CLKPS

Reserved

C2CSEL

C1CSEL

TCNT1

TCNT2

TCRA

TCRB

Res

TAOUT TBEN TAEN TBEDG TAEDG MDSEL

PC87570-ICC/VUL 数据表(PDF) 114 Page - National Semiconductor (TI)

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