PC87570-ICCSLASHVUL datasheet(115/168 Pages) NSC

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Multi-Function 16-Bit Timer (MFT16)

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Bit 4 - TA Enable (TAEN)

Enables TA to function either as a preset input, or as a

PWM output, depending on the mode of operation. If the

bit is set (1), while operating in the “Dual Input Capture”

mode (Mode 2), a transition on TA causes TCNT1 to be

preset to FFFFh. In the remaining modes of operation

setting TAEN enables TA to function as a PWM output.

See Table 14-3 on page 113 for additional information.

Bit 5 - TB Enable (TBEN)

If set (1), and while operating in “Dual Input Capture

Mode” (Mode 2), or “Input Capture + Timer Mode”

(Mode 4), a transition on TB causes the corresponding

timer/counter to be preset to FFFFh. In mode 2 TCNT1

is preset to FFFFh, while in mode 4 TCNT2 is preset to

FFFFh. The bit has no effect while operating in any

mode than other mode 2 or mode 4. See Table 14-3 on

page 113 for additional information.

Bit 6 - TA Output Data (TAOUT)

This bit contains the value of the TA output when TA is

used as a PWM output. When set (1), TA is high. If

cleared TA, is low. The bit is set and cleared by the hard-

ware, and thus reflects the status of TA. You can read

or write the bit at any time. Note that if the hardware at-

tempts to toggle the bit at the same time as the user

software writes to the bit, the software write takes pre-

cedence over the hardware update. The bit has no ef-

fect when TA is used as an input.

14.5.8

Timer Interrupt Control Register (TICTL)

The TICTL Register is a byte-wide read/write register. It

contains the interrupt enable bit and associated interrupt

pending bits for the four timer interrupt sources.

Bit 0 - Timer Interrupt Source A Pending (TAPND)

If set (1), indicates that an interrupt condition, as shown

in Table 14-2, has occurred. This bit can be set by both

the hardware and the user. You can not clear the bit (0)

directly, but must be cleared via the “Timer Interrupt

Clear” register. A write of 0 by the user software is ig-

nored. The bit is cleared (0) on reset.

Bit 1 - Timer Interrupt Source B Pending (TBPND)

Same as TAPND but for a different condition, as shown

in Table 14-2.

Bit 2 - Timer Interrupt Source C Pending (TCPND)

Same as TAPND but for a different condition, as shown

in Table 14-2.

Bit 3 - Timer Interrupt Source D Pending (TCPND)

Same as TAPND but for a different condition, as shown

in Table 14-2.

Bit 4 - Timer Interrupt A Enable (TCPND)

When set (1), enables a system interrupt based on the

occurrence of a condition as listed in Table 14-2. When

cleared (0), no system interrupt occurs, but the associ-

ated pending flag TAPND is still set. The bit can be set

or cleared by the user software at any time.

Bit 5 - Timer Interrupt A Enable (TBIEN)

Same as TAIEN, but for a condition listed in Table 14-2

which causes the TBPND flag to be set by the hardware.

Bit 6 - Timer Interrupt A Enable (TCIEN)

Same as TAIEN, but for a condition listed in Table 14-2

which causes the TCPND flag to be set by the hard-

ware.

Bit 7 - Timer Interrupt A Enable (TDIEN)

Same as TAIEN, but for a condition listed in Table 14-2

which causes the TDPND flag to be set by the hard-

ware.

14.5.9

Timer Interrupt Clear Register (TICLR)

The TICLR Register is an byte-wide write-only register. It

controls the clear of the pending flags TAPND, TBPND,

TCPND and TDPND located in the TICTRL register.

Bit 0 - Timer Pending A Clear (TACLR)

When written to a 1, causes the TAPND flag to be

cleared (0). When written to a 0, the bit has no effect on

TAPND; thus, the previous value of TAPND is main-

tained.

Bit 1 - Timer Pending B Clear (TBCLR)

Has identical functionality to TACLR, but affects the

TBPND flag.

Bit 2 - Timer Pending C Clear (TCCLR)

Has identical functionality to TACLR, but affects the

TCPND flag.

Bit 3 - Timer Pending D Clear (TDCLR)

Has identical functionality to TACLR, but affects the

TDPND flag.

TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND

3210

Res

TDCLR

TCCLR

TBCLR

TACLR

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