AD9546SLASHPCBZ datasheet(103/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 103 of 205

CLOCK

OUTPUT

BURST

PATTERN

TRIGGER

FALLING EDGE

TERMINATES

PERIODIC BURST

START

PATTERN

GENERATION

BURST

PATTERN

BURST

PATTERN

BURST

PATTERN

BURST

PATTERN

TIME

Figure 72. Periodic Gapped Clock Signal

Q DIVIDER

OUTPUT

CLOCK

OUTPUT

Q DIVIDER PERIOD (PER ITS INPUT CLOCK AND DIVIDE RATIO)

CLOCK SEGMENT = 6

GAP SEGMENT = 10

TRIGGER

TIME

PULSES

STALL

ABSENT PULSES

END OF

BURST

END OF

FINAL

BURST

Figure 73. Stalling a Periodic Gapped Clock Signal

N Shot Triggering

The N shot trigger signal originates from one of two sources.

•

Bit 0 of Register 0x2101 or Register 0x2201

•

An external signal applied via an Mx pin

In either case, a Logic 1 constitutes a trigger event. In general,

the user must apply Logic 1 to trigger the N shot generators and

then return the trigger source to Logic 0. Otherwise, holding

the trigger source in a Logic 1 state indefinitely may lead to

unwanted retriggering of the N shot generators on subsequent

distribution synchronization events (see the Distribution

Output Clock Synchronization section).

The N shot generators respond to the trigger signal based on

Bit 6 of Register 0x10D3 or Register 0x14D3. As described in

the N Shot Pattern Generation section, Bit 6 makes the trigger

input of the N shot generators edge or level sensitive for

generating burst or periodic gapped clock signals, respectively (per

Figure 71 and Figure 72).

The trigger mechanism for delivering a trigger signal to the

N shot generators appears in the upper left section of Figure 68.

The N shot generators support two triggering methods: direct

and retimed.

To select the desired triggering method, use Bit 0 of

(default) selects direct, whereas Logic 1 selects retimed. For a

description of Bit 4 of Register 0x10D6 in Figure 68, see the

Modulation Trigger section.

For the direct triggering method, the trigger signal applies

directly to the trigger input of the N shot generators. Thus, the

trigger signal is the trigger event.

Note that in the following paragraphs, the terms slowest and

fastest appear in reference to the output clock signal of the Q

dividers. Slowest and fastest refers to the largest and smallest Q

divider phase offset value, respectively (see the Initial Phase Offset

section).

For the retimed triggering method, the trigger signal routes to

the N shot retime block instead of directly to the N shot

generators. The rising edge of the trigger signal initializes the

retiming block such that the retiming block waits for the rising

edge of the slowest Q divider enabled for N shot operation

(user specified). The trigger signal, qualified by the rising edge

of the slowest Q divider, constitutes a retimed trigger event.

The retiming block sends a trigger signal to the N shot

generators coincident with the retimed trigger event as shown in

Figure 81.

The retimed trigger event occurs with a latency of three rising

edges of the slowest Q divider. Furthermore, when using the

retimed trigger mechanism, the associated Q dividers must

have a divide ratio of at least 32. A minimum setup time of

48 Q divider input half cycles is required between the retiming

output (slowest) and the subsequent N shot enabled output

(fastest).

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