AD9546SLASHPCBZ datasheet(106/205 Pages) AD

106 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 106 of 205

MODULATION CONTROLLER

MODULATOR A

MODULATOR B

MODULATOR C

OUT

SYNC

OUT

MODULATION

BLOCK

N SHOT ENBL

TRIGGER

MODE

TRIGGER

MODE

STEP

TRIGGER

MODE

STEP

SIGA

SNCA

INA

INB

INC

SYNC

SIGB

SNCB

SIGC

SNCC

SIGAA

SIGBB

SIGCC

Q0A

Q0AA

Q0B

Q0BB

Q0C

Q0CC

TRIGGER

MODE

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. REGISTER ADDRESSES SHOWN ARE SPECIFIC TO Q DIVIDER Q0x (WHERE x = A, AA, B, BB, C, OR CC),

PLL CHANNEL 0, AND MODULATOR A

REG 0x10C1 TO 0x10C0,

BITS[15:0]

REG 0x10C5 TO 0x10C2,

BITS[27:0]

REG 0x10CF, BIT 1

REG 0x10CF, BIT 2

REG 0x10CF,

BIT 0

REG 0x10CF,

BIT 3

Figure 74. Block Diagram of Embedded Clock Modulation Controller

TIME

NOMINAL

(50%)

Δt

MODULATION PERIOD (

tMOD)

NOMINAL

(50%)

MODULATION MAGNITUDE

(D =

Δt/tQ)

Q DIVIDER

OUTPUT PERIOD (

tQ)

Figure 75. Modulation Magnitude and Period

AD9546/PCBZ 数据表(PDF) 106 Page - Analog Devices

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