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HC705JJ7GRS/D 数据表(PDF) 157 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 157 Page - NXP Semiconductors |
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157 / 230 page  Programmable Timer Introduction MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 General Release Specification Programmable Timer Figure 11-1. Programmable Timer Overall Block Diagram TMRH ($0018) TMRL ($0019) 16-BIT COUNTER ÷ 4 INTERNAL (OSC ÷ 2) TIMER CONTROL REGISTER TIMER REQUEST RESET CLOCK INTERRUPT ACRH ($001A) ACRL ($001B) 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) PIN I/O LOGIC PB4 AN4 TCMP PB3 AN3 TCAP EDGE SELECT & DETECT TIMER STATUS REGISTER $0012 $0013 INTERNAL DATA BUS LOGIC INPUT SELECT MUX CPF2 FLAG ICEN CONTROL BIT BIT FROM ANALOG SUBSYSTEM ICRH ($0014) ICRL ($0015) D C Q ANALOG COMP 1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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