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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HC705JJ7GRS/D 数据表(PDF) 158 Page - NXP Semiconductors |
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HC705JJ7GRS/D 数据表(HTML) 158 Page - NXP Semiconductors |
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158 / 230 page  Programmable Timer General Release Specification MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0 Programmable Timer 11.3 Timer Registers (TMRH and TMRL) The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 11-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter. Figure 11-2. Programmable Timer Block Diagram The timer registers (TMRH and TMRL) shown in Figure 11-3 are read- only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC. TMRH ($0018) TMR LSB 16-BIT COUNTER ÷ 4 INTERNAL (OSC ÷ 2) TIMER CONTROL REG. TIMER REQUEST OVERFLOW (TOF) RESET CLOCK INTERRUPT TMRL ($0019) TIMER STATUS REG. $0012 $0013 INTERNAL ($FFFC) DATA READ TMRH READ TMRL READ LATCH BUS Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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