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HC705JJ7GRS/D 数据表(PDF) 162 Page - NXP Semiconductors

部件名 HC705JJ7GRS/D
功能描述  Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7) or 28-Pin Package (MC68HC705JP7)
PDF  230 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

HC705JJ7GRS/D 数据表(HTML) 162 Page - NXP Semiconductors

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Programmable Timer
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Programmable Timer
11.5 Input Capture Registers (ICRH and ICRL)
The input capture function is a means to record the time at which an
event occurs. The source of the event can be the change on an external
pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in the
analog subsystem. The ICEN bit in the analog subsystem control
register (ACR) at $001D selects which source is the input signal. When
the input capture circuitry detects an active edge on the selected source,
it latches the contents of the free-running timer counter registers into the
input capture registers as shown in Figure 11-6.
NOTE:
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set
when using voltage comparator 2 to trigger the input capture function
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the selected input signal.
Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal.
Figure 11-6. Timer Input Capture Block Diagram
ICRH ($0014)
16-BIT COUNTER
÷ 4
INTERNAL
(OSC
÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
INPUT CAPTURE (ICF)
RESET
CLOCK
INTERRUPT
ICRL ($0015)
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
READ
ICRH
READ
ICRL
LATCH
BUS
EDGE
SELECT
& DETECT
LOGIC
PB3
AN3
TCAP
INPUT
SELECT
MUX
CPF2
FLAG
ICEN
CONTROL
BIT
BIT
FROM
ANALOG
SUBSYSTEM
INTERNAL
DATA
BUS
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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