HC705JJ7GRSSLASHD datasheet(161/230 Pages) NXP

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Programmable Timer

Alternate Counter Registers (ACRH and ACRL)

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Programmable Timer

The ACRL latch is a transparent read of the LSB until a read of the

ACRH takes place. A read of the ACRH latches the LSB into the ACRL

location until the ACRL is again read. The latched value remains fixed

even if multiple reads of the ACRH take place before the next read of the

ACRL. Therefore, when reading the MSB of the timer at ACRH, the LSB

of the timer at ACRL must also be read to complete the read sequence.

During power-on reset (POR), the counter is initialized to $FFFC and

begins counting after the oscillator startup delay. Because the counter is

16 bits and preceded by a fixed prescaler, the value in the counter

repeats every 262,144 internal bus clock cycles (524,288 oscillator

cycles).

Reading the ACRH and ACRL in any order or any number of times does

not have any effect on the 16-bit free-running counter or the TOF flag bit.

NOTE:

To prevent interrupts from occurring between readings of the ACRH and

ACRL, set the I bit in the condition code register (CCR) before reading

ACRH and clear the I bit after reading ACRL.

$001A

Bit 7

654321

Bit 0

Read:

Bit 15

Bit 8

Write:

Reset:

11111111

$001B

Bit 7

654321

Bit 0

Read:

Bit 7

654321

Bit 0

Write:

Reset:

11111100

= Unimplemented

Figure 11-5. Alternate Counter Registers (ACRH and ACRL)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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