H8SX1663 datasheet(397/1158 Pages) RENESAS

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 345 of 1102

REJ09B0294-0100

The transfer direction is decided by the DIRS bit in DACR which specifies an external device with

the

DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an

external memory (DSAR) to an external device with the

DACK pin. When DIRS = 1, data is

transferred from an external device with the

DACK pin to an external memory (DDAR). The

settings of registers which are not used as the transfer source or destination are ignored.

The

DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The

DACK signal is low active.

The

TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is

output in one bus cycle. When an idle cycle is inserted before the bus cycle, the

TEND signal is

also output in the idle cycle.

Figure 7.5 shows an example of timing charts in single address mode and figure 7.6 shows an

example of operation in single address mode.

LSI

Data flow

External

address

bus

External

data

bus

DMAC

DACK

DREQ

External

memory

External device

with

DACK

Figure 7.4 Data Flow in Single Address Mode

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