H8SX1663 datasheet(399/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 7 DMA Controller (DMAC)

Rev.1.00 Jun. 07, 2006 Page 347 of 1102

REJ09B0294-0100

7.5.2

Transfer Modes

(1) Normal Transfer Mode

In normal transfer mode, one data access size of data is transferred at a single transfer request. Up

to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer

mode.

The

TEND signal is output only in the last DMA transfer. The DACK signal is output every time a

transfer request is received and a transfer starts.

Figure 7.7 shows an example of the signal timing in normal transfer mode and figure 7.8 shows

the operation in normal transfer mode.

Read

Write

Read

Write

DMA transfer

cycle

Last DMA

transfer cycle

Bus cycle

Auto request transfer in dual address mode:

External request transfer in single address mode:

TEND

DMA

DREQ

Bus cycle

DACK

Figure 7.7 Example of Signal Timing in Normal Transfer Mode

H8SX1663 数据表(PDF) 399 Page - Renesas Technology Corp