H8SX1663 datasheet(120/1158 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev.1.00 Jun. 07, 2006 Page 68 of 1102

REJ09B0294-0100

3.2.2

System Control Register (SYSCR)

SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets

external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.

Bit

Bit Name

Initial Value

R/W

Note: * The initial value depends on the startup mode.



R/W



R/W

MACS

R/W



R/W

FETCHMD

R/W



Undefined*

EXPE

Undefined*

R/W

RAME

R/W

Bit

Bit Name

Initial Value

R/W



R/W



R/W



R/W



R/W



R/W



R/W

DTCMD

R/W



R/W

Bit

Bit Name

Initial

Value

R/W

Descriptions



R/W

Reserved

These bits are always read as 1. The write value should

always be 1.

MACS

R/W

MAC Saturation Operation Control

Selects either saturation operation or non-saturation

operation for the MAC instruction.

0: MAC instruction is non-saturation operation

1: MAC instruction is saturation operation



R/W

Reserved

This bit is always read as 1. The write value should

always be 1.

FETCHMD 0

R/W

Instruction Fetch Mode Select

This LSI can prefetch an instruction in units of 16 bits or

32 bits. Select the bus width for instruction fetch

depending on the used memory for the storage of

programs*

0: 32-bit mode

1: 16-bit mode

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