H8SX1663 datasheet(116/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 64 of 1102

REJ09B0294-0100

2.9

Processing States

The H8SX CPU has five main processing states: the reset state, exception-handling state, program

execution state, bus-released state, and program stop state. Figure 2.16 indicates the state

transitions.

• Reset state

In this state the CPU and internal peripheral modules are all initialized and stopped. When the

RES input goes low, all current processing stops and the CPU enters the reset state. All

interrupts are masked in the reset state. Reset exception handling starts when the

RES signal

changes from low to high. For details, see section 4, Exception Handling.

The reset state can also be entered by a watchdog timer overflow when available.

• Exception-handling state

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or

trap instruction. The CPU fetches a start address (vector) from the exception handling vector

table and branches to that address. For further details, see section 4, Exception Handling.

• Program execution state

In this state the CPU executes program instructions in sequence.

• Bus-released state

The bus-released state occurs when the bus has been released in response to a bus request from

a bus master other than the CPU. While the bus is released, the CPU halts operations.

• Program stop state

This is a power-down state in which the CPU stops operating. The program stop state occurs

when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details,

see section 23, Power-Down Modes.

Note:

* A transition to the reset state occurs whenever the

RES signal goes low.

A transition can also be made to the reset state when the watchdog timer overflows.

Reset state*

Exception-handling

state

Request for exception

handling

End of exception

handling

Program execution

state

Bus-released state

Bus

request

End of bus request

Program stop state

SLEEP instruction

Interrupt

request

Bus request

End of

bus request

RES = high

RES = low

Figure 2.16 State Transitions

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