H8SX1663 datasheet(113/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 61 of 1102

REJ09B0294-0100

2.8.11

Extended Memory Indirect—@@vec:7

This mode can be used by the JMP and JSR instructions. The operand value is a branch address,

which is the contents of a memory location pointed to by the following operation result: the sum

of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4.

The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to

H'0003FF in other modes. In assembler notation, an address to store a branch address is specified.

In normal mode, the memory location is pointed to by word-size data and the branch address is 16

bits long. In other modes, the memory location is pointed to by longword-size data. In middle or

advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00).

2.8.12

Effective Address Calculation

Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The

lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign

extended) according to the CPU operating mode.

The valid bits in middle mode are as follows:

• The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for

the transfer and operation instructions.

• The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended

for the branch instructions.

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