H8SX1663 datasheet(111/1158 Pages) RENESAS

111 / 1158 page

Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 59 of 1102

REJ09B0294-0100

2.8.7

Immediate—#xx

The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the

instruction code.

This addressing mode has short formats in which 3- or 4-bit immediate data can be used.

When the size of immediate data is less than that of the destination operand value (byte, word, or

longword) the immediate data is zero-extended.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit

number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code,

for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction

code, for specifying a vector address.

2.8.8

Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,

which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of

the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC

contents. The PC contents to which the displacement is added is the address of the first byte of the

next instruction, so the possible branching range is

−126 to +128 bytes (−63 to +64 words) or

−32766 to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting

value should be an even number. In advanced mode, only the lower 24 bits of this branch address

are valid; the upper 8 bits are all assumed to be 0 (H'00).

2.8.9

Program-Counter Relative with Index Register—@(RnL.B, PC), @(Rn.W, PC),

or @(ERn.L, PC)

This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address,

which is the sum of the following operation result and the 32-bit address of the PC contents: the

contents of an address register specified by the register field in the instruction code (RnL, Rn, or

ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is

the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of

this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).

H8SX1663 数据表(PDF) 111 Page - Renesas Technology Corp

H8SX1663 数据表(HTML) 111 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载