H8SX1663 datasheet(108/1158 Pages) RENESAS

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Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 56 of 1102

REJ09B0294-0100

2.8.2

The operand value is the contents of the memory location which is pointed to by the contents of an

address register (ERn). ERn is specified by the register field of the instruction code.

In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are

valid and the upper 8 bits are all assumed to be 0 (H'00).

2.8.3

or @(d:32, ERn)

The operand value is the contents of a memory location which is pointed to by the sum of the

contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the

16-bit displacement is sign-extended when added to ERn.

This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the

displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the

operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data.

2.8.4

Index Register Indirect with Displacement—@(d:16,RnL.B), @(d:32,RnL.B),

@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)

The operand value is the contents of a memory location which is pointed to by the sum of the

following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an

address register (RnL, Rn, ERn) specified by the register field in the instruction code are zero-

extended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction

code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data,

ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4,

respectively.

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