H8SX1663 datasheet(105/1158 Pages) RENESAS

105 / 1158 page

Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 53 of 1102

REJ09B0294-0100

Table 2.11

System Control Instructions

Instruction

Size

Function

TRAPA

—

Starts trap-instruction exception handling.

RTE

—

Returns from an exception-handling routine.

RTE/L

—

Returns from an exception-handling routine, restoring data from the stack

to multiple general registers.

SLEEP

—

Causes a transition to a power-down state.

B/W

#IMM

→ CCR, (EAs) → CCR, #IMM → EXR, (EAs) → EXR

Loads immediate data or the contents of a general register or a memory

location to CCR or EXR.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and memory. The upper 8 bits are valid.

LDC

→ VBR, Rs → SBR

Transfers the general register contents to VBR or SBR.

B/W

CCR

→ (EAd), EXR → (EAd)

Transfers the contents of CCR or EXR to a general register or memory.

Although CCR and EXR are 8-bit registers, word-size transfers are

performed between them and memory. The upper 8 bits are valid.

STC

VBR

→ Rd, SBR → Rd

Transfers the contents of VBR or SBR to a general register.

ANDC

CCR

∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with immediate data.

ORC

CCR

∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate data.

XORC

CCR

⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with immediate data.

NOP

—

+ 2 → PC

Only increments the program counter.

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