H8SX1663 datasheet(101/1158 Pages) RENESAS

101 / 1158 page

Section 2 CPU

Rev.1.00 Jun. 07, 2006 Page 49 of 1102

REJ09B0294-0100

Table 2.7

Logic Operation Instructions

Instruction

Size

Function

AND

B/W/L

(EAd)

∧ #IMM → (EAd), (EAd) ∧ (EAs) → (EAd)

Performs a logical AND operation on data between immediate data,

general registers, and memory.

B/W/L

(EAd)

∨ #IMM → (EAd), (EAd) ∨ (EAs) → (EAd)

Performs a logical OR operation on data between immediate data,

general registers, and memory.

XOR

B/W/L

(EAd)

⊕ #IMM → (EAd), (EAd) ⊕ (EAs) → (EAd)

Performs a logical exclusive OR operation on data between immediate

data, general registers, and memory.

NOT

B/W/L

∼ (EAd) → (EAd)

Takes the one's complement of the contents of a general register or a

memory location.

Table 2.8

Shift Operation Instructions

Instruction

Size

Function

SHLL

SHLR

B/W/L

(EAd) (shift)

→ (EAd)

Performs a logical shift on the contents of a general register or a memory

location.

The contents of a general register or a memory location can be shifted by

1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by

any bits. In this case, the number of bits is specified by 5-bit immediate

data or the lower 5 bits of the contents of a general register.

SHAL

SHAR

B/W/L

(EAd) (shift)

→ (EAd)

Performs an arithmetic shift on the contents of a general register or a

memory location.

1-bit or 2-bit shift is possible.

ROTL

ROTR

B/W/L

(EAd) (rotate)

→ (EAd)

Rotates the contents of a general register or a memory location.

1-bit or 2-bit rotation is possible.

ROTXL

ROTXR

B/W/L

(EAd) (rotate)

→ (EAd)

Rotates the contents of a general register or a memory location with the

carry bit.

1-bit or 2-bit rotation is possible.

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