H8SX1663 datasheet(257/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 205 of 1102

REJ09B0294-0100

6.7

Byte Control SRAM Interface

The byte control SRAM interface is a memory interface for outputting a byte select strobe during

a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to

the SRAM that has the upper byte select and the lower byte select strobes such as

UB and LB.

The operation of the byte control SRAM interface is the same as the basic bus interface except

that: the byte select strobes (

LUB and LLB) are output from the write strobe output pins (LHWR

and

LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in

the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the

RD/

WR signal is used as write enable.

6.7.1

Byte Control SRAM Space Setting

Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte

control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified

as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid

and byte control SRAM interface cannot be used.

6.7.2

Data Bus

The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM

space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit

access space cannot be specified as the byte control SRAM space.

For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid.

Access size and data alignment are the same as the basic bus interface. For details, see section

6.5.6, Endian and Data Alignment.

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