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H8SX1663 数据表(PDF) 300 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 300 Page - Renesas Technology Corp |
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300 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 248 of 1102 REJ09B0294-0100 Table 6.23 Pin States during DRAM Refresh Cycle Pin State A17 to A0 Hold the value of the previous bus cycle D15 to D0 Hi-Z RAS Used for refresh control LUCAS, LLCAS Used for refresh control WE High AS High RD High BS High RD/ WR High The RAS signal can be delayed for one to three clock cycles by setting bits RCW1 and RCW0 in REFCR. The pulse width of the RAS signal is changed by bits RLW2 to RLW0 in REFCR. The settings of bits RCW1, RCW0, and RLW2 to RLW0 are effective only for a refresh cycle. The precharge time set by bit TPC1 and TPC0 is effective for a refresh cycle. Figure 5.55 shows a timing for setting bits RCW1 and RCW0 TR p TR r TR rw TR c1 TR c2 B φ RAS LUCAS LLCAS BS RD/ WR High High Figure 6.55 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW2 = 0, RLW1 = 0, RLW0 = 0) |
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