H8SX1663 datasheet(315/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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315 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 263 of 1102

REJ09B0294-0100

6.11.8

Controlling Precharge Cycle

When the time between the PALL or PRE command and the subsequent ACTV or REF command

does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits

TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency

of this LSI so that the number of Tp cycles can be optimal.

Figures 6.65 and 6.66 show a timing example when the two Tp cycles are inserted.

Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle.

Address bus

Row address

Column address

Precharge-sel

RAS

CAS

CKE

PALL

ACTV

READ

NOP

DQMLU

DQMLL

D7 to D0

RD/

D15 to D8

Row

address

High

Figure 6.65 Read Timing Example of Two Precharge Cycles

(TPC1 = 0, TPC0 = 1, CAS Latency = 2)

H8SX1663 数据表(PDF) 315 Page - Renesas Technology Corp