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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX1663 数据表(PDF) 317 Page - Renesas Technology Corp |
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H8SX1663 数据表(HTML) 317 Page - Renesas Technology Corp |
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317 / 1158 page  Section 6 Bus Controller (BSC) Rev.1.00 Jun. 07, 2006 Page 265 of 1102 REJ09B0294-0100 6.11.9 Controlling Clock Suspend Insertion When the SDRAM space is read, the read data settling cycle can be inserted for one cycle using the clock suspend mode. To enter the clock suspend mode, set the CKSPE bit in SDCR and the OEE bit in DRAMCR to 1and enable the CKE pin. Figure 6.67 shows a read timing example when CKSPE = 1. T p T r T c1 T cl T c2 T c1 T cl T c2 T sp T sp SD φ CS Precharge-sel Address bus Row address Row address Column address 1 Column address 2 RAS CAS WE CKE PALL ACTV READ READ NOP NOP DQMLU DQMLL D7 to D0 BS RD/ WR D15 to D8 Figure 6.67 Read Timing Example when CKSPE = 1 (CAS Latency = 2) |
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