H8SX1663 datasheet(321/1158 Pages) RENESAS

部件名	H8SX1663

功能描述	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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321 / 1158 page

Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 269 of 1102

REJ09B0294-0100

RAS

CAS

DQMU

DQML

CLK

CKE

A11 (BA1)

A10 (BA0)

DQ15 to DQ0

RAS

CAS

DQMLU

DQMLL

OE/CKE

A12

A11

A10

D15 to D0

This LSI

(Address shifted by 8 bis)

64-Mbit synchronous DRAM

(1 Mwords

× 16 bits × 4 banks)

10-bit column address

Row address:

A11 to A0

Column address:

A9 to A0

Bank select address:

A11/A10

Figure 6.71 Connection Example of DQM Byte/Word Control

6.11.12

Fast-Page Access Operation

Besides an accessing method in which this LSI outputs a row address every time it accesses the

SDRAM (called full access or normal access), some SDRAMs have a fast-page mode function in

which fast speed access can be achieved by modifying only a column address with the same row

address output when consecutive accesses are made to the same row address.

The fast-page mode can be used by setting the BE bit in DRAMCR to 1.

H8SX1663 数据表(PDF) 321 Page - Renesas Technology Corp

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