AD9547SLASHPCBZ datasheet(28/104 Pages) AD

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AD9547

Rev. 0 | Page 28 of 104

FAULTED

VALID

FORCE VALIDATION

TIMEOUT

REF FAULT

REF MONITOR

BYPASS

REF MONITOR

OVERRIDE

REFERENCE VALIDATION LOGIC

(4 COPIES, 1 PER REFERENCE INPUT)

REFERENCE

MONITOR

VALIDATION TIMER

TIMEOUT

Figure 32. Reference Validation Override

Reference Validation Override Control

ability to override the reference validation logic, enabling a

certain level of troubleshooting capability. Each of the four

input references has a dedicated block of validation logic, as

shown in Figure 32. The state of the valid signal at the output

defines a particular reference as valid (1) or not valid (0), which

includes the validation period (if activated) as prescribed by the

validation timer. The override controls are the three control bits

on the left side of the diagram.

The main feature to note is that when faulted = 1, the output latch

is reset, which forces valid = 0 (indicating an invalid reference),

regardless of the state of any other signal. Under the default con-

dition (that is, all three control bits are set to 0), the reference

monitor is the primary source of the validation process. This is

because, under the default condition, the ref fault signal from the

reference monitor is identical to the faulted signal.

The function of the faulted signal is fourfold.

•

When faulted = 1, valid = 0, regardless of the state of any

other control signal. Therefore, faulted = 1 indicates an

invalid reference.

•

When the faulted signal transitions from 0 to 1 (that is, from

not faulted to faulted), the validation timer is momentarily

reset, which means that, when it is enabled, it must exhaust its

full counting sequence before it expires.

•

When faulted = 0 (that is, the reference is not faulted), the

validation timer is allowed to perform its timing sequence.

When faulted = 1 (that is, the reference is faulted), the

validation timer is reset and halted.

•

The faulted signal passes through an inverter, which converts

it to a not faulted signal that appears at the input of the valid

latch. This allows the valid latch to capture the state of the

not faulted signal when the validation timer expires.

The reference monitor bypass control bit (Address 0x0A10) enables

bypassing of the reference fault signal generated by the reference

monitor. When the reference monitor bypass bit = 1, the state of the

faulted signal is dictated by the reference monitor override control

bit. This is useful when the user relies on an external reference

monitor rather than the internal monitor resident in the device.

The user programs the reference monitor override bit based on

the status of the external monitor. On the other hand, when the

reference monitor bypass bit = 0, the reference monitor override

control bit (Address 0x0A0F) allows the user to manually test

the operation of both the valid latch and the validation timer.

In this case, the user relies on the signal generated by the internal

reference monitor (reference fault) but uses the reference monitor

override bit to emulate a faulted reference. That is, when the

reference monitor override bit = 1, faulted = 1, but when the

reference monitor override bit = 0, faulted = reference fault.

In addition, the user can emulate a timeout of the validation timer

via the force validation timeout control register at Address 0x0A0E.

Writing a Logic 1 to this autoclearing bit triggers the valid latch,

which is identically equivalent to a timeout of the validation timer.

REFERENCE PROFILES

The AD9547 has eight independent profile registers. A profile

parameters. Each of the four input references can be assigned to

any one of the eight profiles (that is, more than one reference can

be assigned to the same profile). The profiles allow the user to

prescribe the specific device functionality that should take effect

when one of the input references assigned to a profile becomes the

active reference. Each profile register has the same format and

stores the following device parameters:

•

Reference priority

•

Reference period value (in femtoseconds (fs))

•

Inner tolerance value (1/tolerance)

•

Outer tolerance value (1/tolerance)

•

Validation timer value (milliseconds (ms))

•

Redetect timer value (milliseconds (ms))

•

Digital loop filter coefficients

•

Reference prescaler setting (R divider)

•

Feedback divider settings (S, U, and V)

•

DPLL phase lock detector threshold level

•

DPLL phase lock detector fill rate

•

DPLL phase lock detector drain rate

•

DPLL frequency lock detector threshold level

•

DPLL frequency lock detector fill rate

•

DPLL frequency lock detector drain rate

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