AD9547SLASHPCBZ datasheet(43/104 Pages) AD

43 / 104 page

AD9547

Rev. 0 | Page 43 of 104

The deterministic delay, expressed as tLATENCY in the following

equation, is a function of the frequency division factor (Qn) of

the channel divider associated with the zero-delay channel.

tLATENCY = (Qn + 4) × tCLK_IN or tLATENCY = (Qn + 5) × tCLK_IN

In addition to deterministic delay, there is random delay (tPROP)

associated with the propagation of the reference signal through

the input reference receiver, as well as the propagation of the

clock signal through the clock distribution logic. The total delay is

tDELAY = tLATENCY + tPROP

The user can compensate for tDELAY by using the device’s phase

offset controls to move the edge timing of the distribution output

signal relative to the input reference edge. One method is to

use the open-loop phase offset registers (Address 0x030D and

Address 0x030E) for timing adjustment. However, be sure to

use sufficiently small phase increments to make the adjustment.

Too large a phase step can result in the clock distribution logic

missing a CLKINx edge, thus disrupting the edge alignment

process. The appropriate phase increment depends on the

transient response of any external circuitry connected between

the DACOUTx and CLKINx pins.

The other method is to use the closed-loop phase offset registers

(Address 0x030F to Address 0x0315) for timing adjustment.

However, be sure to use a sufficiently small phase vs. time profile.

Changing the phase too quickly can cause the DPLL to lose lock,

thus ruining the edge alignment process. Note that the AD9547

phase slew limit register (Address 0x0316 and 0x0317) can be

used to limit the rate of change of phase automatically, thereby

mitigating the potential loss-of-lock problem.

To guarantee synchronization of the output dividers, it is

important to make any edge timing adjustments after the

synchronization event. Furthermore, when making timing

adjustments, the distribution outputs can be disabled and then

renabled after the adjustment is complete. This prevents the

device from generating output clock signals during the timing

adjustment process.

Note that the form of zero-delay synchronization described here

does not track propagation time variations within the distribution

clock input path or the reference input path (on or off chip) over

temperature, supply, and so on. It is strictly a one-time synchro-

nization event.

Synchronization Mask

Each output channel has a dedicated synchronization mask bit

(Register 0x0402, Bits[1:0]). When the mask bit associated with

a particular channel is set, that channel does not respond to the

synchronization signal. This allows the device to operate with

the masked channels active and the unmasked channels stalled

while they wait for a synchronization pulse.

AD9547/PCBZ 数据表(PDF) 43 Page - Analog Devices

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