AD9547SLASHPCBZ datasheet(55/104 Pages) AD

55 / 104 page

AD9547

Rev. 0 | Page 55 of 104

Data Transfer Process

The master initiates data transfer by asserting a start condition.

This indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first) plus an R/W bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (0 =

write, 1 = read).

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other devices

on the bus remain idle while the selected device waits for data to be

read from or written to it. If the R/W bit = 0, the master (trans-

mitter) writes to the slave device (receiver). If the R/W bit = 1,

the master (receiver) reads from the slave device (transmitter).

See the

section for the command format.

Data Transfer Format

Data is then sent over the serial bus in the format of nine clock

pulses, one data byte (eight bits) from either master (write mode)

or slave (read mode) followed by an acknowledge bit from the

receiving device. The number of bytes that can be transmitted

per transfer is unrestricted. In write mode, the first two data

bytes immediately after the slave address byte are the internal

memory (control registers) address bytes with the high address

byte first. This addressing scheme gives a memory address up to

216 − 1 = 65,535. The data bytes after these two memory address

bytes are register data written into or read from the control regi-

sters. In read mode, the data bytes after the slave address byte are

When all data bytes are read or written, stop conditions are estab-

lished. In write mode, the master (transmitter) asserts a stop

condition to end data transfer during the 10th clock pulse following

the acknowledge bit for the last data byte from the slave device

(receiver). In read mode, the master device (receiver) receives the

last data byte from the slave device (transmitter) but does not pull

SDA low during the ninth clock pulse. This is known as a no

acknowledge bit. When receiving the no acknowledge bit, the slave

device knows the data transfer is finished and enters idle mode.

The master then takes the data line low during the low period

before the 10th clock pulse, and high during the 10th clock pulse

to assert a stop condition.

A start condition can be used in place of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

3 TO 7

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

SDA

SCL

MSB

Figure 60. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)

3 TO 7

ACK FROM

MASTER RECEIVER

NO ACK FROM

MASTER RECEIVER

SDA

SCL

Figure 61. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)

Data Transfer Format

In write byte format, the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.

Slave

Address

RAM Address

High Byte

RAM Address

Low Byte

RAM

Data 0

RAM

Data 1

RAM

Data 2

In send byte format, the send byte protocol is used to set up the register address for subsequent reads.

Slave Address

RAM Address High Byte

RAM Address Low Byte

In receive byte format, the receive byte protocol is used to read the data bytes from RAM starting from the current address.

Slave Address

RAM Data 0

RAM Data 1

RAM Data 2

Read byte format combines the format of the send byte and the receive byte formats.

Slave

Address

RAM

Address

High Byte

RAM

Address

Low Byte

Slave

Address

RAM

Data

RAM

Data

RAM

Data

AD9547/PCBZ 数据表(PDF) 55 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

AD9547/PCBZ 数据表(PDF) 55 Page - Analog Devices

AD9547/PCBZ 数据表(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载